Dr. Arun Kumar Sunaniya

Arun Kumar Sunaniya
Associate Professor
Email: arun@ei.nits.ac.in
Date of Joining: 19/11/2014
Academic/Industrial Experience: 17+ years
Google Scholar: Click Here










  • B. E. from GEC Ujjain, M. P. (2002)
  • M. Tech. from SGSITS, Indore, M. P. (2008)
  • Ph. D. from MANIT, Bhopa, M. P. (2014)


  • Nov 2019-till date: Assistant Professor, Grade-I (8000 GPA), NIT Silchar, Silchar, Assam.
  • Aug 2016 to Nov 2019: Assistant Professor, Grade-II (7000 GPA), NIT Silchar, Silchar, Assam.
  • Nov 2014 to Aug 2016: Assistant Professor, Grade-II (6000 GPA), NIT Silchar, Silchar, Assam.
  • Before joining NIT Silchar worked in some private engineering institutes in Indore & Bhopal M. P.


  • Semiconductor Devices
  • Digital Integrated Circuits
  • Signal & Image Processing


Dr. Arun Kumar Sunaniya obtained his B.E degree from Govt. Engineering College Ujjain, M.P. in 2002. He completed his M.Tech degree from SGSITS, Indore in 2008. In 2014, he was awarded the Ph.D. degree from the MANIT, Bhopal (M. P.). He joined the National Institute of Technology Silchar as an Assistant Professor in the Department of Electronics and Instrumentation Engineering in Nov. 2014. His research interests include modern semiconductor devices, Digital and analog VLSI Systems, and image processing for medical and non-medical applications. Until now, he has published a few research articles in SCI, Scopus journals & conferences, and some book chapters. He is an active reviewer of various reputed journals and has reviewed some papers. He is supervising Ph.D. scholars in the area of semiconductor devices for solar cells and image processing.



  1. A Method For Performing Image Sharpening On The Basis Of Local Intensity Variation, Republic of South Africa Patent, 202022103269, Granted, (31/05/2023).
  2. Himangshu Deka, Arun Kumar Sunaniya, Pratima Agarwal, “An apparatus for the design of a short pin diode, single-sided silicon heterojunction solar cell” Patent number 202022103269, German Patent (Status: Granted 17/06/2022)




  • Member, DPC, 10th Aug. 2023-till date.
  • Member, DPPC, 10th Aug. 2023-till date.
  • Chairman, Departmental syllabus up-gradation committee, 10th Aug. 2023-till date.
  • Member, DUPC 20th Aug. 2021-9th Aug. 2023.
  • Member, DPMC, 20th Aug. 2021-9th Aug. 2023.
  • Member (Secretary), Departmental syllabus up-gradation committee, 20th Aug. 2021-9th Aug. 2023.
  • Additional departmental bodies/cells: Member, Industrial Training & Internships 20th Aug. 2021-20th Aug. 2023.
  • Additional departmental bodies/cells: Member MIS & Internet, Website 20th Aug. 2021-20th Aug. 2023.
  • Faculty In-charge: Simulation Design & Fabrication Lab. (EI 318), 20th Aug. 2021-till date.
  • Faculty In-charge: Digital Electronics Lab. (EI 216), 20th Aug. 2021-till date.
  • Faculty In-charge: Design, Simulation & Development Lab. (EI 5104), 20th Aug. 2021-till date.
  • Member Secretary, DPPC, EIE, 2014-2019
  • Associate Warden, Ist year Hostel, 2016-2018



  1. Himangshu Deka, Arun Kumar Sunaniya, Pratima Agarwal, “Simulation studies on MoS2 (n)/a-Si:H (i)/c-Si (p)/MoO3 heterojunction solar cells using one sided short diode approximation”, Solar Energy, Elsevier, vol. 263, pp. 1-9, (2023).
  2. Moudgollya, Rhittwikraj, Arun Kumar Sunaniya, Abhishek Midya, and Jayasree Chakraborty. “A multi features based background modeling approach for moving object detection.” Optik 260 (2022): 168980. https://doi.org/10.1016/j.ijleo.2022.168980
  3. Subhajit Das and A. K. Sunaniya, “FPGA Implementation of High-fidelity Hybrid Reversible Watermarking Algorithm.”, Elsevier, Journal of Microprocessor and Microsystems, MICPRO-D-21-00592. https://doi.org/10.1016/j.micpro.2022.104442 (2022).
  4. Deka, Himangshu, Arun Kumar Sunaniya, and Pratima Agarwal. “Design and Simulation of Highly Efficient One-Sided Short PIN Diode Silicon Heterojunction Solar Cell.” IEEE Journal of Photovoltaics (2021).
  5. A. Sekhar, S. Biswas, R. Hazra, A. K. Sunaniya, A. Mukherjee and L. Yang, “Brain tumor classification using fine-tuned GoogLeNet features and machine learning algorithms: IoMT enabled CAD system,” in IEEE Journal of Biomedical and Health Informatics, vol. 26(3), pp. 983-991, 2022. doi: 10.1109/JBHI.2021.3100758. (2021),
  6. Subhajit Das, A. K. Sunaniya, R. Maity and N. P. Maity, “Efficient FPGA Implementation and Verification of Difference Expansion Based Reversible Watermarking with Improved Time and Resource Utilization.”, Journal of Microprocessor and Microsystems, Vol-83, p.103092, (2021).
  7. Subhajit Das, A. K. Sunaniya, R. Maity and N. P. Maity, “Efficient FPGA Implementation of Corrected Reversible Contrast Mapping Algorithm for Video Watermarking.”, Journal of Microprocessor and Microsystems, Vol-76, p-103092, (2020).
  8. Subhajit Das, A. K. Sunaniya, R. Maity and N. P. Maity, “Parallel Hardware Implementation of Efficient Embedding Bit Rate Control Based Contrast Mapping Algorithm For Reversible Watermarking”, IEEE Access, Vol-8, pp-69072-69095, (2020).
  9. Rhittwikraj Moudgollya, Abhishek Midya, Arun Kumar Sunaniya, Jayasree Chakraborty “Dynamic background modeling using intensity and orientation distribution of video sequence” Multimedia Tools and Applications, Springer Nature, Volume 78, Issue 16, pp 22537–22554, ISSN: 1380-7501 (Print), 1573-7721 (Online), https://doi.org/10.1007/s11042-019-7575-7, I.F 1.541. (2019).
  10. Neeraj Kumar Singh, Arun Kumar Sunaniya, “An Adaptive Image Sharpening Scheme based on Local Intensity Variations” Springer Journal of Signal, Image and Video Processing ISSN: 1863-1703 (Print); 1863-1711 (Online); https://doi.org/10.1007/s11760-016-1022-2 , IF 1.643, (2016)
  11. Arun Kumar Sunaniya, Kavita Khare, “Design of Resistor less 45nm Switched Inverter Scheme (SIS)ADC & Clocked SIS ADC for Low Noise and Improved Power Delay Product” European Journal of Scientific Research, vol.111, no.4, ISSN no.1450- 216x, pp.510-523, September 2013.
  12. Arun Kumar Sunaniya, Kavita Khare, “Design of Improved Resistor less 45nm Switched Inverter Scheme (SIS) Analog to Digital Converter” International journal of VLSI design & Communication Systems, vol.4, no.3, ISSN no.0976-1357, pp.109-124, June 2013.
  13. Arun Kumar Sunaniya, Kavita Khare, “Design & Comparison of Resistor less 45nm Switched Inverter Scheme (SIS) ADCs for Low Power & High Speed Applications” The Mediterranean Journal of Electronics and Communications, vol.9 no.2, ISSN no.1744-2400, pp.561-568, April 2013.
  14. Arun Kumar Sunaniya, Kavita Khare, “Design of 45nm Switched Inverter Scheme (SIS) ADCs for Low Power and High Speed Applications” International Journal of Computer Application, vol.68, no.5, ISSN no.0975 – 8887, pp.26-33, April 2013.
  15. Arun Kumar Sunaniya, Kavita Khare, “A Low power 50 nm Technology Based CMOS Inverter with Sleep Transistor Scheme” International Journal of Computer Science Engineering & Technology, vol.1, no.9, ISSN no.2231-0711, pp.560-562, October 2011.
  16. Arun Kumar Sunaniya, Kavita Khare, “A Design Comparison of Low Power 50 nm Technology Based Inverter with Sleep Transistor and MTCMOS Scheme”, International Journal of Engineering Science and Technology, vol.3, no.10, ISSN no.0975-5462, pp.7744-7753, October 2011.


  1. S. Singh, Das O. P,  Sunaniya Arun Kumar (57192195023) Pandey S.  K. “Simulation of Optimum Stored Charge in SONOS FLASH Memory using Silvaco TCAD” (2022) ICDCS 2022 – 2022 6th International Conference on Devices, Circuits and Systems, pp. 174 – 177, DOI: 10.1109/ICDCS54290.2022.9780682
  2. Sudarsan Sahoo, Kuldeep Kushwah, Arun Kumar Sunaniya “Health Monitoring of Wind Turbine Blades through Vibration Signal Using Advanced Signal Processing Techniques”2020 Advanced Communication Technologies and Signal Processing (ACTS), pp 1-6, Silchar, India, 2020, doi: 10.1109/ACTS49415.2020.9350405
  3. Subhajit Das, Neha Fegde, Arun Kumar Sunaniya “VLSI based Architecture for Modified Reversible Contrast Mapping based Reversible Image Watermarking using Xilinx System Generator” International Conference on Recent Trends on Electronics & Computer Science (ICRTECS 2019), NIT Silchar (ECE), (Accepted)
  4. Anand Sevda, Arun Sunaniya & R.S.Gamad “Design and optimization of noise, power consumption and slew rate of a two stage CMOS Op-Amp” International Conf. on advances in computing (ICAC-08), 21-22 Feb.2008.
  5. Arun Sunaniya, Anand Sevda, R.S.Gamad & Gaurav Gupta “Design of a variable size Comparator for Flash A/D Converter with Increased Speed & Reduced Power Consumption.” National conf. MIT, Ujjain 22-23 Feb 2008.
  6. Anand Sevda, Arun Kumar Sunaniya, R.S. Gamad & Manish Jain “Design & Optimization of Noise & Power Consumption of a Two-stage CMOS Op-Amp” National conf. SGSITS, Indore, India, Page 402-406, 18-20 Dec. 2007.


  1. Deka, H., Sunaniya, A.K., Agarwal P., “A Numerical Study on a c-Si(P) Substrate- Based Homo-Hetero Junction Solar Cell” Sustainable Energy Generation and Storage, Springer, Singapore (2023).
  2. Das S., Sunaniya A.K. (2020) A Study on Reversible Image Watermarking Using Xilinx System Generator. In: Das A., Nayak J., Naik B., Pati S., Pelusi D. (eds) Computational Intelligence in Pattern Recognition. Advances in Intelligent Systems and Computing, vol 999. Springer, Singapore. https://doi.org/10.1007/978-981-13-9042-5_19.
  3. Das S., Sunaniya A.K. (2020) A Comparative Study of Reversible Video Watermarking Using Automatic Threshold Adjuster and Non-feedback-Based DE Method. In: Elçi A., Sa P., Modi C., Olague G., Sahoo M., Bakshi S. (eds) Smart Computing Paradigms: New Progresses and Challenges. Advances in Intelligent Systems and Computing, vol 766. Springer, Singapore. https://doi.org/10.1007/978-981-13-9683-0_9


  • Coordinator of One-week GIAN course on Digital Payments & Digital Currency: Challenges & Solutions for India at NIT Silchar from 20-25 February, 2023
  • Coordinator of Two weeks GIAN course on Innovation & Technology Enterprise: Idea to Entrepreneurship at NIT Silchar from 30th July-10th August, 2018.
  • Coordinator of TEQIP-III sponsored One week short-term course on Recent Trends in Communication, Signal Processing and Solid State Devices at NIT Silchar from 13-17 March 2018.
  • Coordinator of TEQIP-II sponsored One week short-term course on Recent Trends in Communication, Signal Processing and VLSI at NIT Silchar from 14-18 March 2017.



Sl. No. Name of the Scholar Status Thesis Title Supervision
 1 Himangshu Deka Submitted (Jun. 2023)  Design and modelling of a-Si/c-Si, MoS2/c-Si heterojunction solar cells and application of low pressure RF sputtered Al2O3 for hydrogenated amorphous silicon based solar photovoltaics Main Supervisor
(Jointly with
Prof. P.
Agarwal, IITG)
2 Rhittwikraj Moudgollya Completed (Sep. 2022) Computationally Efficient Moving Object Detection and Tracking Under Challenging Background Conditions Sole Supervisor
3 Subhajit Das Completed (Jan. 2022)  Design and Implementation of Efficient FPGA based Hardware Architectures for Improved Reversible Watermarking Algorithms Sole Supervisor
4 Anjana Bharti Subba Ongoing Medical Image processing Sole Supervisor
5 Gaurav Gupta Ongoing Salient Object Detection Sole Supervisor



S.No Student Dissertation Topic Status Year
1 Saifuddin Barbhuiya Design and performance evaluation of an improved efficiency compound semiconductor solar cell Completed 2015-17
2 Sudem Daimary  Impulsive Noise Detection and Removal in Color Image Completed 2015-17
3 Sarful Alam  Design & performance analysis of Gallium Arsenide (GaAs) Hetro-junction Bipolar Transistor solar cell Completed 2016-18
 4 Nayan Jyoti Boro Efficiency Enhancement And Reflectance Reduction Of Single Junction Compound Semiconductor Solar Cell  Completed  2016-18
5 Neha Fegde FPGA Implementation of Efficient VLSI Architecture for Improved Reversible Watermarking Algorithms Completed 2017-19
 6 Kuldeep Kushwah  Health monitoring of wind turbine blades through vibration and acoustic emission signals using machine learning techniques Completed  2018-2020
7 Ardhendu Sekhar Brain Tumor Classification using Transfer Learning Completed 2019-21
8 Samdar Singh Modeling and simulation of optimum stored charge in SONOS flash memory using Silvaco TCAD Completed 2020-22

Awards and Recognitions

  • Active reviewer of some SCI, SCIE & Scopus journals.
  • Active reviewer of some conferences.
  • Active Reviewer (Journals): IEEE Journals of Biomedical Health & Informatics, Advances in nano research.
  • Active Reviewer (Conferences): SCES 2020 organized by MNNIT Allahabad, E2A (EIE, NIT Silchar) 2021, 2022, IEEE SILCON 2022, MNDCS 2022 (ECE, NIT Silchar).
  • Session Chair (Conferences): E2A (EIE, NIT Silchar) 2021, 2022, IEEE SILCON 2022, MNDCS 2022 (ECE, NIT Silchar).
  • UBA Cell, Member, 2019-till date.

Invited Talks

  • G. H. Raisoni Institute of Engineering and Technology, Nagpur (Mah.), 2021
  • Mahakal Institute of Technology, Ujjain (M.P.) 2020
  • THDC Institute of Hydropower Engineering & Technology, Tehri, Uttarakhand. 2019


About Ranjay Hazra

Dr. Ranjay Hazra completed his schooling at Don Bosco School Park Circus, Kolkata in 2005. He obtained his B.Tech degree in Electronics and Communication Engineering from SRM University, Chennai in 2009. After which he received his M.Tech degree from West Bengal University of Technology, Kolkata in 2011. In 2016, he was awarded Ph.D. degree in Communication Systems from IIT Roorkee. He is currently working as an Assistant Professor in the Department of Electronics and Instrumentation Engineering, NIT Silchar since August 2016.